1. Field of the invention
The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory organized in the form of a serial access memory having a serial port.
2. Description of related art
Referring to FIG. 1, there is shown a conceptional diagram showing a fundamental construction of the semiconductor memory organized in the form of a serial access memory having a serial port.
The shown memory includes a memory cell array 100 formed of a matrix of a number of memory cells (not shown) having a number of rows and a number of clumns, and a sense amplifier group 102 including a number of sense amplifiers each of which is connected to a pair of complementary bit lines of a corresponding one of the columns.
The memory cell array 100 is associated with a row decoder 104 and a column decoder 106, which are coupled to an address buffer 108 so as to receive respective corresponding portions of an address held in the address buffer 108. Furthermore, all the bit lines of the memory cell array 100 are connected through a transfer gate group 110 to a data register group 112, which is in turn connected to a serial input/output buffer 114 of a serial port 116.
With the above mentioned arrangement, data read from the memory cell array 100 is transferred in parallel through the transfer gate group 110, and temporarily held in the data register group 112 in parallel. The data temporarily held in the data register group 112 in serially outputted through the serial input/output buffer 114. On the other hand, data to be written to the memory cell array 100 is serially transferred through the serial input/output buffer 114 and temporarily held in the data register group 112. The data temporarily held in the data register group 112 is transferred in parallel through the transfer gate group 110, and written to the memory cell array 100.
The above mentioned construction and operation are merely fundamental construction and operation. However, since a detailed construction and operation of the serial access memory is known to persons in the art, explanation of the detailed construction, including control signal lines, and the detailed operation, will be omitted.
Turning to FIG. 2, there is shown a block diagram of a portion of a data register circuit incorporated for example in the serial access memory shown in FIG. 1. The shown data register circuit portion includes a data register 13 having a pair of input/output terminals connected to a drain of a pair of NMOS transistors 14 and 15, respectively, which have their gate connected to a data transfer control signal line 18. A source of the NMOS transistors 14 and 15 are connected through a sense amplifier 16 to a pair of complementary bit lines 216 and 217 extending from a memory cell array 17. Thus, the pair of NMOS transistors 14 and 15 constitute a transfer gate between the data register 13 and the memory cell array 17.
In this shown data register circuit portion, it may be considered that the data register 13 constitutes a minimum register stage of the data register group 112, the pair of NMOS transistors 14 and 15 correspond to a unitary transfer gate of the transfer gate group 110, the sense amplifier 16 forms a unitary sense amplifier of the sense amplifier 102, and the memory cell array 17 corresponds to the memory cell array 100.
With the above mentioned arrangement, if the data transfer control signal line are 18 brought to a high level 18, the NMOS transistors 14 and 15 are turned on, so that a plurality of data bits are simultaneously transferred to the data register group, from which the plurality of data bits are serially read out through the serial input/output port. Thus, it is possible to perform a serial data reading from the memory cell array 17. Similarly, it is possible to perform a serial data writing to the memory cell array 17.
In the above mentioned conventional serial access semiconductor memory, as will be apparent from FIG. 2, one data register 13 is provided for one sense amplifier 16 in one-to-one relation, so as to constitute one unitary data register circuit. Accordingly, a number of unitary data register circuits each of which is formed as shown in FIG. 2 are associated to the memory cell array. In other words, there exist unitary data register circuits of the number corresponding to the number of complementary bit line pairs, namely, the number of sense amplifiers provided in the memory cell array.
This is disadvantageous in that if the capacity of the semiconductor memory is increased, the circuit scale of the semiconductor memory is correspondingly increased. In addition, with advance of microminiaturization in a semiconductor memory manufacturing process, if the degree of microminiaturization in the memory cell and the degree of microminiaturization in peripheral circuits including the data buffers become different, the arrangement of the conventional serial access semiconductor memory will make it difficult to locate the data buffers in association with the memory cell array.